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Publications - Roman Bartosinski


Books and chapters (3)
1. * Petr Honzík, Roman Bartosinski, Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora: Video Processing: Foreground Recognition in the ASVP Platform. Smart Multicore Embedded Systems, 159-175. Springer, New York 2014.   Download
2. * Roman Bartosinski, Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora: The Architecture and the Technology Characterization of an FPGA-Based Customizable Application-Specific Vector Coprocessor (ASVP). Smart Multicore Embedded Systems, 45-77. Springer, New York 2014.   Download
3. * Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosinski: UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs. Circuits & Systems . Springer, New York 2013.

Journal articles (1)
1. * Rudolf Matoušek, Martin Daněk, Zdeněk Pohl, Roman Bartosinski, Petr Honzík: Reconfigurable System-on-a-Chip. Syndicated 5:2 (2005), 1-3.

Conference papers (17)
1. * Jaroslav Sýkora, Lukáš Kohout, Roman Bartosinski, Leoš Kafka, Martin Daněk, P. Honzík: The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor. Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 62-67. IEEE, Tallinn, ESTONIA 2012.   Download
2. * Jaroslav Sýkora, Roman Bartosinski, Lukáš Kohout, Martin Daněk, P. Honzík: Reducing Instruction Issue Overheads in Application-Specific Vector Processors. Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012, 600-607. Conference Publishing Services, Izmir 2012.   Download
3. * Roman Bartosinski, Martin Daněk, Jaroslav Sýkora, Lukáš Kohout, P. Honzík: Video Surveillance Application Based on Application Specific Vector Processors. Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, 248-255. Electronic Chips & Systems design Initiative, Gières 2012.   Download
4. * Roman Bartosinski, Martin Daněk, Jaroslav Sýkora, Lukáš Kohout, P. Honzík: Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs. Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, 375-376. Electronic Chips & Systems design Initiative, Gières 2012.   Download
5. * Roman Bartosinski: The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator. ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, 1657-1660. IEEE, Praha 2011.   Download
6. * Martin Daněk, J.-M. Philippe, Roman Bartosinski, Petr Honzík, Ch. Gamrat: Self-Adaptive Networked Entities for Building Pervasive Computing Aschitectures. International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008, 94-105. Springer, Heidelberg 2008.   Download
7. * Martin Daněk, Jiří Kadlec, Roman Bartosinski, Lukáš Kohout: Increasing the Level of Abstraction in FPGA-based Designes. International Conference on Field Programmable Logic and Applications, 5-10. Kirchhoff Institute for Physics, Heidelberg 2008.   Download
8. * Roman Bartosinski, Z. Hanzálek, P. Stružka, L. Waszniowski: Integrated Environment for Embedded Control Systems Design. Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium, 1-8. IEEE Computer Society, Los Alamitos, CA 2007.
9. * Jiří Kadlec, Roman Bartosinski, Martin Daněk: Accelerating MicroBlaze Floating Point Operations. Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), 621-624. IEEE, Delft 2007.
10. * P. Stružka, L. Waszniowski, Roman Bartosinski, T. Bysterský: Design of Control Application Using Processor Expert Blockset. Technical Computing Prague 2007, 1-8. Humusoft, Praha 2007.
11. * Roman Bartosinski, Martin Daněk, Petr Honzík, Jiří Kadlec: Modelling Self-Adaptive Networked Entities in Matlab/Simulink. Technical Computing Prague 2007, 1-8. Humusoft, Praha 2007.
12. * Roman Bartosinski, Jiří Kadlec: Simulation of MCU hardware peripherals. Technical Computing Prague 2007, 1-7. Humusoft, Praha 2007.
13. * Roman Bartosinski, Jiří Kadlec: Hardware co-simulation with communication server from MATLAB/Simulink. Technical computing Prague 2006. 14th annual conference proceedings, 13-20. Humusoft, Prague 2006.
14. * Roman Bartosinski, Z. Hanzálek, L. Waszniowski, P. Stružka: Processor Expert Enhances Matlab Simulink Facilities for Embedded Software Rapid Development. Emerging Technologies and Factory Automation 2006, 1-4. IEEE, Piscataway 2006.
15. * Roman Bartosinski, P. Stružka, L. Waszniowski: Peert-blockset for processor export and matlab/simuling integration. Technical Computing Prague 2005 : 13th Annual Conference Proceedings, 1-8. VŠCHT, Praha 2005.
16. * Roman Bartosinski, Martin Daněk, Petr Honzík, Rudolf Matoušek: Dynamic reconfiguration in FPGA-based SoC designs. ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, 35-38. HiPEAC Network of Excellence, Ghent 2005.
17. * Roman Bartosinski, Martin Daněk, Petr Honzík, Rudolf Matoušek: Dynamic reconfiguration in FPGA-based SoC designs. Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems, 129-136. University of West Hungary, Sopron 2005.

Other publications (3)
1. * Leoš Kafka, Roman Bartosinski, Martin Daněk: Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs. ÚTIA AV ČR, Praha 2007.
3. * Roman Bartosinski, Martin Daněk, Petr Honzík, Rudolf Matoušek: Dynamic reconfiguration in FPGA-based SoC designs. Abstract. FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, 274. ACM, Monterey 2005.

Miscellaneous (4)
1. * Roman Bartosinski, Martin Daněk, Jaroslav Sýkora, Lukáš Kohout: Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs. 2012.
2. * Roman Bartosinski: Knihovna Proseccor Expert-Simulink. 2008.
3. * Roman Bartosinski: Processor Expert AutoSAR-Simulink Library. 2008.