Home

Publications - Jiří Kadlec


Books and chapters (4)
1. * Ch. Gamrat, J. M. Philippe, Ch. Jesshope, A. Shafarenko, L. Bisdounis, U. Bondi, A. Ferrante, J. Cabestany, M. Hübner, J. Pärsinnen, Jiří Kadlec, Martin Daněk, B. Tain, S. Eisenbach, M. Auguin, J. P. Diguet, E. Lenormand, J. L. Roux: AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies. Reconfigurable Computing. From FPGAs to Hardware/Software Codesign, 149-184. Springer, Londýn 2011.   Download
2. * T. Dulík, Z. Křivka, Jiří Kadlec, M. Bližňák, V. Budíková, O. Jirák, N. Olšarová, J. Trbušek, Z. Vašíček: Virtuální laboratoř pro vývoj aplikací s mikroprocesory a FPGA. CERM, Brno 2011.   Download
3. * E. Hillerová, Jiří Kadlec: Czech Republic, Information Society Technology. ÚTIA AV ČR, Praha 1999.
4. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Parallel implementation of restricted parameter tracking. Institute of Mathematics and its Applications Conference Series. 49. Mathematics in Signal Processing, 315-325. Clarendon Press, Oxford 1994.

Journal articles (29)
1. * C. Sau, C. Rinaldi, L. Pomante, F. Palumbo, G. Valente, T. Fanni, M. Martinez, F. van der Linden, T. Basten, M. Geilen, G. Peeren, Jiří Kadlec, J. Pekka, L. Bulej, F. Barranco, J. Saarinen, T. Säntti, M. K. Zedda, V. Sanchez, S. T. Nikkhah, D. Goswami, G. Amat, L. Maršík, M. van Helvoort, L. Medina, Z. Al-Ars, A. de Beer: Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project. Microprocessors and Microsystems 87. Elsevier.   Download
2. * J. Hoozemans, J. Van Straten, T. Viitanen, A. Tervo, Jiří Kadlec, Z. Al-Ars: ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA. Journal of Signal Processing Systems for Signal Image and Video Technology 91:1 (2019), 61-73. Springer.   Download
3. * V. Coufalová, D. Zsapková Haringová, Jiří Kadlec: Účast České republiky ve společných technologických iniciativách ARTEMIS, ENIAC a ECSEL. Echo 2016, 12-14.   Download
7. * Jiří Kadlec: Elektronika pro zvýšení bezpečnosti malých městských automobilů. Elektro 2013, 21-21. FCC Public.   Download
8. * Jiří Kadlec, K. Nedvědová: Artemis JU and Eniac JU Projects with Czech Participation. Automa, 6-9.   Download
9. * Jiří Kadlec: Czech Companies Involved in the ARTEMIS Programme. Automa, 4-5.   Download
12. * Zdeněk Pohl, Milan Tichý, Jiří Kadlec: Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA. EURASIP Journal on Advances in Signal Processing 2008 (2008), 1-11.   Download
13. * J. N. Coleman, C. I. Softley, Jiří Kadlec, R. Matoušek, Milan Tichý, Zdeněk Pohl, Antonín Heřmánek, N. F. Benschop: The European Logarithmic Microprocessor. IEEE Transactions on Computers 57:4 (2008), 532-546.   Download
14. * Jiří Kadlec, E. Vaculíková: ARTEMIS - šance pro výzkum v oboru vestavných systémů - polemika. Automa 13:10 (2007), 13-15.
15. * Martin Daněk, Petr Honzík, Jiří Kadlec, Zdeněk Pohl, Rudolf Matoušek: Platforma s částečnou dynamickou rekonfigurací FPGA. Automa 12:5 (2006), 40-43.
16. * Jiří Kadlec, E. Vaculíková: Podpora projektů informační a komunikační techniky v 7.rámcovém programu EU pro výzkum. Automa 13:5 (2006), 82-83.
17. * Jiří Kadlec, S. Chappel: Implementing floating-point DSP. Embedded Magazine 2:3 (2006), 12-14.   Download
18. * Martin Daněk, Petr Honzík, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl: Reconfigurable system on programmable chip platform. ATMEL Applications Journal, 9-12.
19. * Jiří Kadlec, V. Albrecht: Význam účasti v projektech EU. Echo 2:2 (2005), 11-13.
20. * Jiří Kadlec: IDEALIST: Jak najít partnery pro projekty IST. Echo, 13.
21. * Jiří Kadlec, Rudolf Matoušek, Antonín Heřmánek, Miroslav Líčko, Milan Tichý: Lattice for FPGAs using logarithmic arithmetic. Electronic Engineering 74:906 (2002), 53-56.
22. * J. N. Coleman, E. I. Chester, C. I. Softley, Jiří Kadlec: Arithmetic on the European Logarithmic Microprocessor. IEEE Transactions on Computers 49:7 (2000), 702-715.
24. * J. Hlavička, Jiří Kadlec: Vstup do evropské informační společnosti - program IST. Automa 6:7 (2000), 105-107.
25. * Jiří Kadlec, Jan Schier: Analysis of a normalized QR filter using Bayesian description of propagated data. International Journal of Adaptive Control and Signal Processing 13:6 (1999), 487-505. Wiley.
26. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: A parallel fixed-point predictive controller. International Journal of Adaptive Control and Signal Processing 11:5 (1997), 415-430. Wiley.   Download
27. * Jiří Kadlec: Transputer implementation of block regularized filtering. Kybernetika 32:3 (1996), 235-250. Ústav teorie informace a automatizace AV ČR, v. v. i..
28. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: The block regularised parameter estimator and its parallelisation. Automatica 31:8 (1995), 1125-1136. Elsevier.   Download
29. * Jiří Kadlec, G. Masarik, D. H. Nguyen: Paralelní počítače a superpočítače dneška. Computer World 10:10 (1991), 18-19.

Conference papers (84)
1. * Raissa Likhonina, Jiří Kadlec, Evženie Uglickich: Hand detection ultrasound based application implemented on the FPGA platform. Book of abstracts. 6th International Caparica Conference on Ultrasonic-based applications from analysis to synthesis, 107-107. PROTEOMASS Scientific Society, Portugal 2023.
2. * L. Pomante, F. Palumbo, C. Rinaldi, G. Valente, C. Sau, T. Fanni, F. Linden, T. Basten, M. Geilen, G. Peeren, Jiří Kadlec, P. Jääskeläinen, M. Martinez, J. Saarinen, T. Säntti, M. Zedda, V. Sanchez, D. Goswami, Z. Al-Ars, A. Beer: Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project. Proceedings - Euromicro Conference on Digital System Design, DSD 2020, 378-385. IEEE, Piscataway 2020.   Download
3. * A. Zaid, T. Basten, A. Beer, M. Geilen, D. Goswami, P. Jääskeläinen, Jiří Kadlec, M. Alejandro, F. Palumbo, G. Peeren, L. Pomante, F. Linden, J. Saarinen, T. Säntti, C. Sau, M. Zedda: The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems. Proceedings of the 16th ACM International Conference on Computing Frontiers, 333-338. ACM Digital Library, New York 2019.   Download
4. * H. Isakovic, R. Grosu, D. Ratasich, Jiří Kadlec, Zdeněk Pohl, S. Kerrison: A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2. Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, 127-140. Springer, Cham 2017.   Download
5. * Raissa Likhonina, Lukáš Kohout, Jiří Kadlec: Camera-to-touchscreen design. Proceedings of 6th International Workshop on Mathematical Models and their Applications (IWMMA’2017), 94-99. Siberian State University of Science and Technology, Krasnojarsk 2017.   Download
6. * Jiří Kadlec: Video Chain Demonstrator on Xilinx Kintex7 FPGA with EdkDSP Floating Point Accelerators. Proceedings 2015 International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XV). IEEE, Piscataway 2015.
7. * Jiří Kadlec: In-circuit, Run-time Compiler of Finite State Machines for the UTIA EdkDSP Customizable Accelerators. Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, 32-33. Politecnico di Milano, Milano 2012.   Download
8. * P. Honzík, Jiří Kadlec: Dynamic Placement Applications into Self Adaptive Network on FPGA. 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), 453-456. Institute of Electrical and Electronics Engineers ( IEEE ), Cottbus 2011.   Download
9. * Jiří Kadlec: Účast ČR ve společných technologických iniciativách ARTEMIS a ENIAC. Hovory s informatiky, 95-113. Ústav informatiky AV ČR, v.v.i, Praha 2011.   Download
10. * Jiří Kadlec, Martin Daněk, Lukáš Kohout: Proposed architecture of configurable, adaptable SoC. The IET Irish Signals and Systems Conference ISSC 2008, 368-373. Institution of Engineering and Technology, Londýn 2008.
11. * Jiří Kadlec: Design Flow for Reconfigurable MicroBlaze Accelerators. 4th International Workshop on Reconfigurable Communication Centric System-on-Chips Workshop Proceedings, 133-140. UPC, Barcelona 2008.
12. * Martin Daněk, Jiří Kadlec, Roman Bartosinski, Lukáš Kohout: Increasing the Level of Abstraction in FPGA-based Designes. International Conference on Field Programmable Logic and Applications, 5-10. Kirchhoff Institute for Physics, Heidelberg 2008.   Download
13. * Jiří Kadlec, Roman Bartosinski, Martin Daněk: Accelerating MicroBlaze Floating Point Operations. Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), 621-624. IEEE, Delft 2007.
14. * Roman Bartosinski, Jiří Kadlec: Simulation of MCU hardware peripherals. Technical Computing Prague 2007, 1-7. Humusoft, Praha 2007.
15. * Roman Bartosinski, Martin Daněk, Petr Honzík, Jiří Kadlec: Modelling Self-Adaptive Networked Entities in Matlab/Simulink. Technical Computing Prague 2007, 1-8. Humusoft, Praha 2007.
16. * Jiří Kadlec, Martin Daněk: Design and verification methodology for reconfigurable designs in Atmel FPSLIC. Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, 79-80. Czech Technical University, Prague 2006.
17. * Roman Bartosinski, Jiří Kadlec: Hardware co-simulation with communication server from MATLAB/Simulink. Technical computing Prague 2006. 14th annual conference proceedings, 13-20. Humusoft, Prague 2006.
18. * Jiří Kadlec: Reconfigurable floating point co-processor for atmel FPSLIC. MAPLD 2005 International Conference Proceedings, 1-12. NASA Official of Logic Design, Washington 2005.
19. * Jiří Kadlec, R. Gook: Floating point controller as a picoblaze network on a single spartan 3 FPGA. MAPLD 2005 International Conference Proceeding, 1-11. NASA Office of Logic Design, Washington 2005.
20. * Zdeněk Pohl, Jiří Kadlec, P. Šůcha, Z. Hanzálek: Performance tuning of interative algorithms in signal processing. Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, 699-702. Academy of Finland, Tampere 2005.
21. * Martin Daněk, Antonín Heřmánek, Petr Honzík, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl: GIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs. ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, 15-18. HiPEAC Network of Excellence, Ghent 2005.
22. * Martin Daněk, Petr Honzík, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl: Reconfigurable system-on-a-programmable-chip platform. Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 21-28. Institute of Informatics SAS, Bratislava 2004.
23. * Zdeněk Pohl, Rudolf Matoušek, Jiří Kadlec, Milan Tichý, M. Líčko: Lattice adaptive filter implementation for FPGA. FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, 246. ACM, Monterey 2003.
24. * Rudolf Matoušek, Zdeněk Pohl, Martin Daněk, Jiří Kadlec: Dynamic reconfiguration of Atmel FPGAs. UK ACM SIGDA 3rd Workshop on Electronic Design Automation, 1-4. University of Southampton, Southampton 2003.
25. * Rudolf Matoušek, Martin Daněk, Zdeněk Pohl, Jiří Kadlec: Dynamic runtime partial reconfiguration in FPGA. ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, 294-298. Technical University, Liberec 2003.
26. * Antonín Heřmánek, Zdeněk Pohl, Jiří Kadlec: FPGA implementation of the adaptive lattice filter. Lecture Notes in Computer Science. 2778. Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, 1095-1098. Springer, Berlin 2003.
27. * Rudolf Matoušek, Zdeněk Pohl, Martin Daněk, Jiří Kadlec: Dynamic reconfiguration of FPGAs. Recent Trends in Multimedia Information Processing. Proceedings, 288-291. Czech Technical University, Prague 2003.
28. * Jan Schier, Jiří Kadlec: Using logarithmic arithmetic for FPGA implementation of the Givens rotations. Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications, 199-204. Universidade de Vigo, Vigo 2003.
29. * Rudolf Matoušek, Milan Tichý, Zdeněk Pohl, Jiří Kadlec, C. Softley: Logarithmic number system and floating-point arithmetics on FPGA. Lecture Notes in Computer Science. 2438. Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 627-636. Springer, Berlin 2002.
30. * R. Matoušek, Z. Pohl, Jiří Kadlec, Milan Tichý, Antonín Heřmánek: Logarithmic arithmetic core based RLS LATTICE implementation. Design, Automation and Test in Europe DATE 02, 271. IEEE, Los Alamitos 2002.
31. * Jiří Kadlec, Milan Tichý, Antonín Heřmánek, Z. Pohl, M. Líčko: Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs. Design, Automation and Test in Europe DATE˙02, 264. IEEE, Los Alamitos 2002.
32. * F. Albu, Jiří Kadlec, N. Coleman, A. Fagan: Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic. Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 2681-2684. IEEE, Orlando 2002.
33. * F. Albu, Jiří Kadlec, N. Coleman, A. Fagan: The Gauss-Seidel Fast Affine Projection algorithm. IEEE Workshop on Signal Processing Systems. Proceedings, 109-114. IEEE, San Diego 2002.
34. * F. Albu, Jiří Kadlec, Antonín Heřmánek, A. Fagan, N. Coleman: Analysis of the LNS implementation of the fast affline projection algorithms. Proceedings of the Irish Signals and Systems Conference 2002. ISSC 2002, 251-255. Institute of Technology, Cork 2002.
35. * F. Albu, Jiří Kadlec, Ch. Softley, Rudolf Matoušek, Antonín Heřmánek, J. N. Coleman, A. Fagan: Implementation of (Normalised) RLS Lattice on Virtex. Lecture Notes in Computer Science. 2147. Field-Programmable Logic and Applications. Proceedings, 91-100. Springer, Berlin 2001.
36. * Jiří Kadlec: Structure estimation for systems described by radial basis functions based on normalized QR filtering. Preprints of the 1st IFAC/IEEE Symposium on System Structure and Control. IFAC, Prague 2001.
37. * Jiří Kadlec, Rudolf Matoušek, Miroslav Líčko: FPGA implementation of logarithmic unit core. Embedded Intelligence 2001, 547-554. Design & Elektronik, Nürnberg 2001.
38. * Jiří Kadlec, Rudolf Matoušek, Antonín Heřmánek, Miroslav Líčko, Ch. Softley: Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1. Celoxica User Conference. Proceedings. Celoxica, Abington 2001.   Download
39. * F. Albu, Jiří Kadlec, A. Fagan, J. N. Coleman: Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic. Advances in Systems Science: Measurement, Circuits and Control. Proceedings, 517-521. WSES Press, Rethymno 2001.
40. * J. N. Coleman, Jiří Kadlec: Extended Precision Logarithmic Arithmetic. Signal Systems and Computers 2000, 34th Asilomar Conference on Signal Systems and Computers. Proceedings, 124-129. IEEE Signal Processing Society, Monterey 2001.
41. * Antonín Heřmánek, Jiří Kadlec, Rudolf Matoušek, Miroslav Líčko, Zdeněk Pohl: Pipelined logarithmic 32bit ALU for Celoxica DK1. Sborník příspěvků 9.ročníku konference MATLAB 2001, 72-80. VŠCHT, Praha 2001.
42. * J. Hlavička, Jiří Kadlec: Vstup českých institucí do evropské informační společnosti. Česko-slovenská konference RUFIS 2000, 27-32. VUT, Brno 2000.
43. * Antonín Heřmánek, Rudolf Matoušek, Miroslav Líčko, Jiří Kadlec: FPGA implementation of logarithmic unit. Sborník příspěvků 8. ročníku konference MATLAB 2000, 84-90. VŠCHT, Praha 2000.
44. * Jan Schier, Jiří Kadlec, M. Moonen: Implementing advanced equalization algorithms using Simulink with embedded Alpha AXP coprocessor. Fifth IMA International Conference on Mathematics in Signal Processing, 11-14. University of Warwick, Warwick 2000.
45. * J. Ondračka, R. Oravec, Jiří Kadlec, E. Cocherová: Simulation of RLS and LMS algorithms for adaptive noise cancellation in MATLAB. Sborník příspěvků 8. ročníku konference MATLAB 2000, 301-305. VŠCHT, Praha 2000.
46. * Christian Vialatte, Jiří Kadlec: RTW support for low cost C31 board. Sborník příspěvků 7. ročníku konference MATLAB '99, 231-237. VŠCHT, Praha 1999.
47. * Christian Vialatte, Jiří Kadlec: RTW support for parallel 64-bit Alpha AXP-based platforms. Sborník příspěvků 7. ročníku konference MATLAB '99, 238-244. VŠCHT, Praha 1999.
48. * Ludvík Tesař, Luděk Berec, G. Dolanc, G. Szederkényi, Jiří Kadlec: A toolbox for model-based fault detection and isolation. European Control Conference. ECC '99. VDI/VDE GMA, Karlsruhe 1999.   Download
49. * Jiří Kadlec, Rudolf Matoušek, Christian Vialatte, J. N. Coleman: Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW. Sborník příspěvků 7. ročníku konference MATLAB '99, 84-90. VŠCHT, Praha 1999.
50. * Jiří Kadlec, Jan Schier: Rapid prototyping of adaptive control algorithms on parallel multiprocessors. Signal Processing Symposium, 115-118. IEEE, Leuven 1998.   Download
51. * Jiří Kadlec: Acceleration of computation-intensive algorithms on parallel Alpha AXP processors. Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, 89-98. ÚTIA AV ČR, Praha 1998.   Download
52. * Miroslav Kárný, Jiří Kadlec, E. L. Sutanto: Quasi-Bayes estimation applied to normal mixture. Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, 77-82. ÚTIA AV ČR, Praha 1998.   Download
53. * Jan Schier, Jiří Kadlec, Josef Böhm: Robust adaptive controller with fine grain parallelism. Preprints of the IFAC Workshop on Adaptive Systems in Control and Signal Processing, 436-441. IFAC, Glasgow 1998.   Download
54. * Jiří Kadlec: Rapid prototyping and parallel processing under MATLAB 5. Wissenschftliche Berichte. 51. Tagungsband. 3. Zittauer Workshop Magnetlagertechnik, 101-104. IPM, Zittau 1997.   Download
55. * Jiří Kadlec: Para-Mat parallel processing under MATLAB. ASIM 11. Simulationstechnik. Tagungsband, 684-687. Vieweg, Braunschweig 1997.
56. * Jiří Kadlec: Parallel processing on Alphas under MATLAB 5. Lecture Notes in Computer Science. 1338. SOFSEM '97: Theory and Practice of Informatics, 440-448. Springer, Berlin 1997.
57. * Jiří Kadlec, Ch. Vialatte: Rapid prototyping and parallel processing under MATLAB 5. MATLAB Conference 1997, 120-125. Kimhua Technology, Seoul 1997.
58. * Petr Nedoma, Jiří Kadlec: Extension of MATLAB parallel accelerator. Computer-Intensive Methods in Control and Signal Processing. Preprints of the 2nd European IEEE Workshop CMP'96, 155-160. ÚTIA AV ČR, Praha 1996.
59. * Jiří Kadlec, F. M. F. Gaston: Identification with directional parameter tracking for high-performance fixed-point implementations. The Sixth Irish DSP and Control Colloquium, 215-222. Techman, Belfast 1995.   Download
60. * Jiří Kadlec, N. Nakhaee: Alpha-Bridge for MATLAB 4. Transputer Applications and Systems '95. Proceedings, 175-189. IOS Press, Harrogate 1995.
61. * J. G. McWhirter, R. L. Walke, Jiří Kadlec: Normalised Givens rotations for recursive least squares processing. VLSI Signal Processing, VIII, 313-322. IEEE, New York 1995.
62. * Jiří Kadlec, N. Nakhaee: Alpha Bridge - high performance computing with MATLAB. Industrial Applications of MATLAB and Simulink for the Analysis of Electro- and Hydro- Mechanical Systems. Preprints, 11-16. Matlab UG, Birmingham 1995.   Download
63. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: The block regularised parameter estimator and its parallelisation. Identification and Optimization, Oriented for Use in Adaptive Control. Preprints, 107-120. ÚTIA AV ČR, Praha 1995.
64. * Jiří Kadlec: Lattice feedback regularised identification. 10th IFAC Symposium on System Identification. Preprints, 277-282. IFAC, Copenhagen 1994.
65. * Jiří Kadlec: Systolic arrays for identification of systems with variable structure. Computer-Intensive Methods in Control and Signal Processing, 123-132. ÚTIA AV ČR, Praha 1994.
66. * Jiří Kadlec: Numerical analysis of normalized RLS filter using a probability description of propagated data. Algorithms and Parallel VLSI Architectures III, 61-72. Elsevier, Amsterdam 1994.
67. * F. M. F. Gaston, Jiří Kadlec, Jan Schier: The block regularized linear quadratic optimal controller. IEE International Conference on Control '94, 1254-1259. IEE, London 1994.   Download
68. * Jiří Kadlec: Direct software bridge MATLAB-transputer boards. Signal Processing Conference. Proceedings, 1601-1604. EUSIPCO, Edinburgh 1994.
69. * Jiří Kadlec: The Lattice-Ladder with Generalized Forgetting. NATO ASI Series. 232. Linear Algebra for Large Scale and Real-Time Applications, 397-398. Kluwer Academic, Leuven 1993.
70. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: A Nonlinear Systolic Filter with Radial Basis Function Estimation. Neural Computing Research and Applications, 183-190. IOP Publ., London 1993.
71. * Jiří Kadlec: Transputer Implementation of Block Regularised Filtering. Progress in Transputer Computing Technology, 1-15. ÚTIA AV ČR, Prague 1993.
72. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Regularised Lattice-Ladder Adaptive Filter. Mutual Impact of Computing Power and Control Theory, 245-257. Plenum Press, New York 1993.
73. * Jiří Kadlec: Structure Determination and Tracking for Parallel Radial Basis Function Based Nonlinear Networks. Innovative Approaches to Modelling and Optimal Control of Large Scale Pipeline Networks, 75-84. ÚTIA AV ČR, Prague 1993.
74. * Jiří Kadlec: The Cell Level Description of Systolic Block Regularised QR Filter. VLSI Signal Processing, 298-306. IEEE, New York 1993.
75. * Petr Nedoma, Jiří Kadlec, Jan Schier: Tools for Implementation of Parallel Algorithms for Adaptive Control and Signal Processing. 4th IFAC International Symposium on Adaptive Systems in Control and Signal Processing. ACASP '92, 727-730. Laboratoire d'Automatique, Grenoble 1992.
76. * Jiří Kadlec: A Joint Criterion for Exponential Directional and Mixed Parameter Tracking. 4th IFAC International Symposium on Adaptive Systems in Control and Signal Processing. ACASP '92, 687-692. Laboratoire d'Automatique, Grenoble 1992.
77. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Regularised Lattice-Ladder Adaptive Filter. IFAC Workshop on Mutual Impact of Computing Power and Control Theory. MICC '92, 143-150. ÚTIA ČSAV, Prague 1992.
78. * Jiří Kadlec: Fast Ladder-Lattice Identification Architecture with Numerically Robust Tracking of Parameters. IFAC Workshop Series. 4. Algorithms and Architectures for Real-Time Control, 105-111. Pergamon Press, Oxford 1992.
79. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Parallel Implementation of Restricted Parameter Tracking. Mathematics in Signal Processing, 86-88. University of Warwick, SouthendonSea 1992.
80. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Systolic Implementation of the Regularized Parameter Estimator. VLSI Signal Processing 6, 520-529. IEEE, New York 1992.
81. * Jiří Kadlec: A Recursive Modified Gram-Schmidt Identification with Directional Tracking of Parameters. Preprints of the 9th IFAC/IFORS Symposium on Identification and System Parameter Estimation, 1707-1712. AKA PRINT Nyomdaipari, Budapest 1991.
82. * Jiří Kadlec: Fast and Adaptive Identification Algorithms Suitable for Neural Network Applications. Neural Nets for System Applications, -. IEE/ÚTIA, Prague 1991.
83. * Jiří Kadlec: Neural Nets for System Applications. IEE/ÚTIA, Praha 1991.
84. * Jiří Kadlec: Identification Algorithms for Parallel Computing Networks with Fixed Point Arithmetic. Neural Nets for System Applications, -. IEE/ÚTIA, Prague 1991.

Other publications (55)
1. * Jiří Kadlec: EDKDSP: Reprogrammable Floating Point Accelerators on KINTEX FPGA with HDMI. 2013 Design, Automation and Test in Europe. , Grenoble 2013.   Download
2. * Jiří Svozil, Leoš Kafka, Jiří Kadlec: PicoBlaze lekce 1: assembler, C překladač a simulační prostředí. ÚTIA AV ČR, Praha 2007.
3. * Jiří Kadlec, Martin Daněk, Jan Schier, Lukáš Kohout, Leoš Kafka, Jan Kloub, Jaroslav Stejskal, Jiří Svozil: Identifikace limitací dosavadních technologií v kontextu projektu VLAM. Research Report 2183. ÚTIA AV ČR, Praha 2007.
4. * Jaroslav Stejskal, Leoš Kafka, Jiří Kadlec: PicoBlaze lekce 2: generování VHDL a implementace systému s procesorem PicoBlaze do FPGA v prostředí Xilinx ISE. ÚTIA AV ČR, Praha 2007.
5. * Jiří Svozil, Jaroslav Stejskal, Leoš Kafka, Jiří Kadlec: PicoBlaze lekce 3: sériová komunikace RS232 a testování IP jader pomocí procesoru PicoBlaze. ÚTIA AV ČR, Praha 2007.
6. * Jiří Kadlec: Embedded Development Environment for a Family of Xilinx FPGA. Regional Conference on Embedded and Ambient Systems Book of Abstracts, 16-16. John von Neumann Computer Society, Budapešť 2007.
7. * Jiří Kadlec: Preparation ARTEMIS and the Czech republic: current status and related issues. Regional Conference on Embedded and Ambient Systems Book of Abstracts, 15-15. John von Neumann Computer Society, Budapešť 2007.
8. * Zdeněk Pohl, Jiří Kadlec: RLS Lattice Demo. ÚTIA AV ČR, Praha 2006.
9. * Jiří Kadlec: Double Precision Simulation Package double-dk-rel2. (Program). ÚTIA AV ČR, Praha 2005.
10. * Jiří Kadlec: Scalable Floating Point Simulation Package float-dk-rel2. (Program). ÚTIA AV ČR, Praha 2005.
11. * Jiří Kadlec, Martin Daněk, Petr Honzík: Reconfigurable 24-Bit Floating-Point Coprocessor Demo. Research Report 2116. ÚTIA AV ČR, Praha 2004.
12. * Jiří Kadlec, Martin Daněk, Petr Honzík: Reconfigurable Scrolling Demo. Research Report 2117. ÚTIA AV ČR, Praha 2004.
13. * Zdeněk Pohl, Jiří Kadlec, Miroslav Líčko, Rudolf Matoušek, Milan Tichý: Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program). ÚTIA AV ČR, Praha 2003.
14. * Rudolf Matoušek, Miroslav Líčko, Jiří Kadlec: European Logarithmic Microprocessor. (Program). ÚTIA AV ČR, Praha 2003.
15. * Zdeněk Pohl, Jiří Kadlec, Milan Tichý: RLS Lattice - Celoxica RC200 Demo. (Program). ÚTIA AV ČR, Praha 2003.
16. * Miroslav Líčko, Radim Matulík, Rudolf Matoušek, Jiří Kadlec: Prototyping Board for CAK. (Program). ÚTIA AV ČR, Praha 2003.
17. * Miroslav Líčko, Jiří Kadlec: An Introduction to the Xilinx System Generator. (Program). ÚTIA AV ČR, Praha 2003.
18. * Miroslav Líčko, Jan Schier, Zdeněk Pohl, Jiří Kadlec, Milan Tichý, Rudolf Matoušek, Antonín Heřmánek: Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping. Research Report 2069. ÚTIA AV ČR, Praha 2002.
19. * Jan Schier, Jiří Kadlec, M. Moonen: Implementing Advanced Equalization Algorithms using Simulink with Embedded Alpha AXP Coprocessor. Research Report 2013. ÚTIA AV ČR, Praha 2001.
20. * Jiří Kadlec, J. N. Coleman: Extended Precision LNS Arithmetic. Research Report 2008. ÚTIA AV ČR, Praha 2001.
21. * J. N. Coleman, E. I. Chester, Ch. Softley, Jiří Kadlec: Arithmetic on the European Logarithmic Microprocessor. Research Report 2012. ÚTIA AV ČR, Praha 2001.
22. * F. Albu, Jiří Kadlec, Ch. Softley, Rudolf Matoušek, Antonín Heřmánek: Implementation of Normalized RLS Lattice on Virtex. Research Report 2040. ÚTIA AV ČR, Praha 2001.
23. * Jiří Kadlec, Rudolf Matoušek, Miroslav Líčko: FPGA Implementation of Logarithmic Unit Core. Research Report 2007. ÚTIA AV ČR, Praha 2001.
24. * Jiří Kadlec: Review and Classification of RLS Array Algorithms for LNS Arithmetics. Research Report 2006. ÚTIA AV ČR, Praha 2001.
25. * F. Albu, Jiří Kadlec, Rudolf Matoušek, Antonín Heřmánek, J. N. Coleman: A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic. Research Report 2035. ÚTIA AV ČR, Praha 2001.
26. * Jiří Kadlec, F. Albu, Ch. Softley, Rudolf Matoušek, Antonín Heřmánek: RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic. Research Report 2036. ÚTIA AV ČR, Praha 2001.
27. * Jiří Kadlec, Antonín Heřmánek, Ch. Softley, Rudolf Matoušek, Miroslav Líčko: 32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1. Research Report 2037. ÚTIA AV ČR, Praha 2001.
28. * J. N. Coleman, Jiří Kadlec, Rudolf Matoušek, Zdeněk Pohl, Antonín Heřmánek: The European Logarithmic Microprocessor - a QRD RLS Applications. Research Report 2038. ÚTIA AV ČR, Praha 2001.
29. * Antonín Heřmánek, Jiří Kadlec, Rudolf Matoušek, Miroslav Líčko, Ch. Softley: Pipelined Logarithmic 32bit ALU for Celoxica DK1. Research Report 2034. ÚTIA AV ČR, Praha 2001.
30. * Jiří Kadlec, A. Barbier, L. de Castellane, L.-P. Gautier, S. Gourguechon, S. Leroy, A. Paturle: Generation of Simulink S-functions. Research Report 1975. ÚTIA AV ČR, Praha 1999.
31. * Jiří Kadlec, Jan Schier: Results of the Global Probability Analysis Approach. Research Report 1926. ÚTIA AV ČR, Praha 1998.
32. * Jiří Kadlec, Jan Schier: HSLA DSP Package. Research Report 1924. ÚTIA AV ČR, Praha 1998.
33. * Jiří Kadlec, Jan Schier: HSLA 3D Monitor Package. Research Report 1925. ÚTIA AV ČR, Praha 1998.
34. * Jiří Kadlec, Jan Schier: Numerical Analysis of a Normalized QR Filter Using Probability Description of Propagated Data. Research Report 1923. ÚTIA AV ČR, Praha 1998.
35. * Jiří Kadlec: [Recenze]. Automatica 31:10 (1995), 1519-1521. Elsevier.
36. * Jiří Kadlec: Lattice Feedback Regularised Identification. Research Report 1788. ÚTIA AV ČR, Praha 1994.
37. * Jiří Kadlec: Structure Determination and Tracking for Parallel Radial Basic Function Based Nonlinear Networks. Research Report 1790. ÚTIA AV ČR, Praha 1994.
38. * Jiří Kadlec: Transputer Implementation of Block Regularised Filtering. Research Report 1791. ÚTIA AV ČR, Praha 1994.
39. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: The Block Regularised Parameter Estimator and Its Parallel Implementation. Research Report 1787. ÚTIA AV ČR, Praha 1994.
40. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Regularised Lattice-Ladder Adaptive Filter. Research Report 1793. ÚTIA AV ČR, Praha 1994.
41. * F. M. F. Gaston, Jiří Kadlec, Jan Schier: The Block Regularised Linear Quadratic Optimal Controller. Research Report 1789. ÚTIA AV ČR, Praha 1994.
42. * Jiří Kadlec: The Cell-Level Description of Systolic Block Regularised QR Filter.. Research Report 1792. ÚTIA AV ČR, Praha 1994.
43. * Jiří Kadlec: Numerical Analysis of a Normalized RLS Filter Using a Probability Description of Propagated Data. Research Report 1818. ÚTIA AV ČR, Praha 1994.
44. * Jiří Kadlec: Numerical analysis of normalized RGS filter by probability description of propagated data. Abstract. Algorithms and Parallel VLSI Architectures. Abstracts, -. Katholieke Universiteit, Leuven 1994.
45. * Jiří Kadlec: Matlab transputer bridge. Abstract. 10th IFAC Symposium on System Identification. Preprints, 31. IFAC, Copenhagen 1994.
46. * Jiří Kadlec: Parallel Normalized Identification Algorithm with Lattice Feedback Regularization. Research Report 1820. ÚTIA AV ČR, Praha 1994.
47. * Jiří Kadlec: [Recenze]. Automatica 30:5 (1994), 917-918. Elsevier.
48. * Jiří Kadlec: Direct Software Bridge MATLAB-Transputer Boards. Research Report 1819. ÚTIA AV ČR, Praha 1994.
49. * Jiří Kadlec: Systolic Arrays for Identification of Systems with Variable Structure. Research Report 1817. ÚTIA AV ČR, Praha 1994.
50. * Jiří Kadlec, F. M. F. Gaston, G. W. Irwin: Parallel Implementation of Restricted Parameter Tracking. Research Report 1/2. Queen's University, Belfast 1993.
51. * Jiří Kadlec: Unified Design of Fast Array Estimators. Research Report 1/6. Queen's University, Belfast 1992.
52. * Jiří Kadlec, Radim Matulík: Terminály pro zrakově postižené. ÚTIA ČSAV, Praha 1990.
53. * Jiří Kadlec: Research and Development of Fast Numerically Stable Algorithms for Recursive Identification of Stochastic Systems and their Fixed Point Implementations. Lehrstuhl für Regelungssysteme und Steuerungstechnik. . RuhrUniversität, Bochum 1989.
54. * Jiří Kadlec, G. Krampe: Bayesian Analysis of System Parameter Variations, Based on Testing of Hypotheses about Forgetting Factors. Lehrstuhl für Regelungssysteme und Steuerungstechnik. . RuhrUniversität, Bochum 1989.
55. * Jiří Kadlec, P. Stammen: Bayesian Recursive Identification of Large Scale Interconnected Stochastic Time Variable Systems, Based on Testing of Hypotheses about Regreession Models. Lehrstuhl für Regelungssysteme und Steuerungstechnik. . RuhrUniversität, Bochum 1989.

Miscellaneous (105)
1. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Support for TE0821 modules with Vitis AI 3.0 DPU. 2024.   Download
2. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout, Raissa Likhonina: Adaptive Lattice Filter on STM32H7 Devices. 2024.   Download
3. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Support for TE0820 modules with Vitis AI 3.0 DPU. 2024.   Download
4. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Support for STM32H573I-DK web server. 2024.   Download
5. * Lukáš Kohout, Jiří Kadlec, Zdeněk Pohl: Support for TE0802-02-2AEV2-A board with Vitis AI 3.0 DPU and VGA display. 2024.   Download
6. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout, Raissa Likhonina: Compilation of Vitis AI 3.0 models for different configurations of AMD DPUs.. 2024.   Download
7. * Lukáš Kohout, Jiří Kadlec, Zdeněk Pohl: Support for TE0802-02-1BEV2-A board with Vitis AI 3.0 DPU and VGA display. 2024.   Download
14. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout, Raissa Likhonina: Data Movers in DTRiMC tool for TE0726 03M 07S board. 2021.   Download
15. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout, Raissa Likhonina: STM32H753 Terminal with TE0723 03 07S 1C Accelerator HW Data Movers. 2021.   Download
16. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout, Raissa Likhonina: STM32H753 Terminal with Zynq Ultrascale+ Accelerator. 2021.   Download
18. * Jiří Kadlec, Raissa Likhonina: DTRiMC tool for TE0726-03M board. 2021.   Download
19. * Jiří Kadlec, Raissa Likhonina: DTRiMC tool for TE0808-09-EG-ES1 module on TEBF0808 carrier board. 2021.   Download
20. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: DTRiMC tool for TE0820-03-4EV-1E module on TE0701-06 carrier board. 2021.   Download
21. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board. 2021.   Download
22. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: DTRiMC tool for TE0820-02-3CG-1E module on TE0701-06 carrier board. 2021.   Download
29. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Arrowhead Compatible Zynq Ultrascale+ Systems with Xilinx SDSoC 2018.2 Support. 2019.   Download
30. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: FP01x8 Accelerator on TE0726-03M. 2019.   Download
31. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Evaluation version of 8xSIMD FP01x8 accelerator for ArduZynq shield. 2019.   Download
32. * Lukáš Kohout, Jiří Kadlec, Zdeněk Pohl: Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module. 2019.   Download
33. * Jiří Kadlec, Lukáš Kohout: Benchmarks for STM32H7 MCUs. 2019.   Download
34. * Jiří Kadlec, Lukáš Kohout: Industrial 40 nm Demonstrator NUCLEO STM32H755ZI-Q. 2019.   Download
37. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Compact Zynq System with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator. 2018.   Download
39. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator. 2018.   Download
40. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: SW Defined Floating Point 8xSIMD EdkDSP IP Serving for Adaptive Noise Cancellation. 2018.   Download
41. * Raissa Likhonina, Jiří Kadlec: Noise Cancellation Using QRD RLS Algorithms. 2018.   Download
42. * Zdeněk Pohl, Lukáš Kohout, Jiří Kadlec: Live Canny Edge Detection. 2018.   Download
43. * Zdeněk Pohl, Lukáš Kohout, Jiří Kadlec: Stereo Demo. 2018.   Download
48. * Zdeněk Pohl, Lukáš Kohout, Jiří Kadlec: ALMARVI Python Camera Platform. 2016.   Download
53. * Jiří Kadlec, Zdeněk Pohl, Lukáš Kohout: Toshiba Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier. 2016.   Download
62. * Lukáš Kohout, Zdeněk Pohl, Jiří Kadlec: EMC2-DP HDMI in HDMI out Platform. 2016.   Download
63. * Jiří Kadlec, D. Zsapková Haringová, E. Sebroňová: Informační a komunikační technologie v programu Horizont 2020.   Download
66. * Jiří Kadlec, D. Zsapková Haringová: Information and communication technologies in Horizon 2020.   Download
75. * J. Lohstroh, E. Schutz, Jiří Kadlec: ARTEMIS Brokerage Event Call 2012.   Download
76. * Jiří Kadlec, Leoš Kafka, J. Svozil: DA Core - Funkční vzorek řadiče D/A převodníku se sběrnicí SPI. 2011.
77. * Jiří Kadlec, Leoš Kafka, J. Stejskal: PWM Core - funkční vzorek generátoru pulzně šířkové modulace. 2011.
78. * Jiří Kadlec, Leoš Kafka, J. Svozil: LCD Core - Funkční vzorek řadiče LCD displeje. 2011.
79. * Jiří Kadlec, Leoš Kafka, J. Svozil: FC Core - funkční vzorek čítače frekvence. 2011.
80. * Jiří Kadlec, Leoš Kafka, J. Svozil: FG Core - funkční vzorek generátoru kmitočtu. 2011.
81. * Jiří Kadlec, Leoš Kafka, J. Svozil: AD Core – Funkční vzorek řadiče A/D převodníku se sběrnicí SPI. 2011.
82. * Jiří Kadlec, Leoš Kafka, J. Stejskal: BASIC IO CORE – Funkční vzorek řadiče elektronického potenciometru. 2011.
85. * Jiří Kadlec, Leoš Kafka, J. Svozil: SPI FLASH Core – Funkční vzorek řadiče paměti SPI Serial Flash. 2011.
86. * Jiří Kadlec, Leoš Kafka, J. Svozil: NOR FLASH Core – Funkční vzorek řadiče paměti Intel StrataFlash. 2011.
87. * Jiří Kadlec, Milada Kadlecová: ARTEMIS / ENIAC Joint Undertaking - Seminář ke 2. výzvě.
88. * Martin Daněk, Jiří Kadlec, B. Nelson: Proceedings 19th International Conference on Field Programmable Logic and Applications (FPL). ÚTIA AV ČR, Praha 2009.
91. * Jiří Kadlec, Milada Kadlecová: ARTEMIS / ENIAC Joint Undertaking Information event.
92. * Jiří Kadlec, Milada Kadlecová, Martin Daněk: Workshop on Embedded Systems Education and Training.
93. * Zdeněk Pohl, Jiří Kadlec, Milan Tichý: Adaptive Noise Canceller Demo based on the LS Lattice Filter. 2007.   Download
95. * Jiří Kadlec, Milada Kadlecová: Robotics in IST FP7.
98. * B. Smith, M. Edin, E. Hillerová, Milada Kadlecová, Dana Heřmánková, Jiří Kadlec: e-2002 e-Work & e-Business Conference. 2002.
99. * T. Grabowiecki, Jiří Kadlec, K. Čerans, T. Pihl, B. Weber, T. Zergoi: Ideal-ist Conference Information Society Technology in the 6th Framework Programme. 2002.
100. * Jiří Kadlec, Dana Heřmánková, K. Trojanowski, P. Drath, M. Schoefield, R. Burak: Managing EC Research Project - Workshop and Brokerage. 2001.
101. * Jiří Kadlec, Milada Kadlecová, R. Pleger, T. Grabowiecki, T. Zergoi, D. Krekels: Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing. 2001.
102. * Jiří Kadlec, Dana Heřmánková, Alice Rektorová, P. Drath, M. Schoefield, P. Martynovicz: Opportunities in the European Union's IST Programme. 2001.
103. * R. Pleger, Jiří Kadlec, T. Grabowiecki, Milada Kadlecová, D. Krekels, Antonín Heřmánek: Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing. 2001.
104. * E. Hillerová, Jiří Kadlec: Informační den k programu IST. Technologické centrum AV ČR, Praha 1999.
105. * E. Hillerová, Jiří Kadlec: Konference k zahájení 5. rámcového programu Evropské unie. MŠMT, Praha 1999.