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Publications - Milan Tichý


Journal articles (5)
1. * Milan Tichý, Jan Schier, D. Gregg: GSFAP Adaptive Filtering Using Log Arithmetic for Resource-Constrained Embedded Systems. ACM Transactions on Embedded Computing Systems 9:3 (2010), 1-31.   Download
2. * J. N. Coleman, C. I. Softley, Jiří Kadlec, R. Matoušek, Milan Tichý, Zdeněk Pohl, Antonín Heřmánek, N. F. Benschop: The European Logarithmic Microprocessor. IEEE Transactions on Computers 57:4 (2008), 532-546.   Download
3. * Zdeněk Pohl, Milan Tichý, Jiří Kadlec: Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA. EURASIP Journal on Advances in Signal Processing 2008 (2008), 1-11.   Download
4. * Jiří Kadlec, Rudolf Matoušek, Antonín Heřmánek, Miroslav Líčko, Milan Tichý: Lattice for FPGAs using logarithmic arithmetic. Electronic Engineering 74:906 (2002), 53-56.
5. * Milan Tichý, P. Zemánek: Performance and tuning of the UNIX operating system. Journal of Electrical Engineering - Elektrotechnický časopis, 74-80. Slovenská technická univerzita v Bratislave.

Conference papers (16)
1. * M. W. Van Tol, Zdeněk Pohl, Milan Tichý: A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms. Advances in Parallel Computing, 579-586. IOS Press BV, Amsterdam 2012.   Download
2. * Zdeněk Pohl, Milan Tichý: Resource Management for the Heterogeneous Arrays of Hardware Accelerators. Proceedings of 21st International Conference on Field Programmable Logic and Applications, 486-489. IEEE, Chania 2011.   Download
3. * Antonín Heřmánek, Michal Kuneš, Milan Tichý: Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique. Proceedings of the International Conference on Field Programmable Logic and Applications, 336-339. IEEE, Piscataway 2010.   Download
4. * Zdeněk Pohl, Milan Tichý: RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator. Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), 774-777. IEEE, Delft 2007.
5. * E. Ozer, Milan Tichý, D. Gregg: Automatic customization of embedded applications for enhanced performance and reduced power using optimizing compiler techniques. Proceedings of the 12th Workshop on Compilers for Parallel Computers. CPC 2006, 16-27. Tórculo Artez Gráfitias, A Coruňa 2006.
6. * Milan Tichý, Jan Schier, D. Gregg: Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA. Reconfigurable Computing: Architecures and Applications. Proceedings of the Second International Workshop ARC, 311-316. Springer, Berlin 2006.
7. * Milan Tichý, Jan Schier, D. Gregg: FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic. Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 342-347. IEEE Signal Processing Society, Calgary 2006.
8. * Zdeněk Pohl, Rudolf Matoušek, Jiří Kadlec, Milan Tichý, M. Líčko: Lattice adaptive filter implementation for FPGA. FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, 246. ACM, Monterey 2003.
9. * Zdeněk Pohl, Jan Schier, Miroslav Líčko, Antonín Heřmánek, Milan Tichý: Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping. Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, 1-6. IEEE Computer Society Press, Los Alamitos 2003.
10. * Miroslav Líčko, Jan Schier, Milan Tichý, M. Kühl: MATLAB/Simulink based methodology for rapid-FPGA-prototyping. Lecture Notes in Computer Science. 2778. Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, 984-987. Springer, Berlin 2003.
11. * Jiří Kadlec, Milan Tichý, Antonín Heřmánek, Z. Pohl, M. Líčko: Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs. Design, Automation and Test in Europe DATE˙02, 264. IEEE, Los Alamitos 2002.
12. * R. Matoušek, Z. Pohl, Jiří Kadlec, Milan Tichý, Antonín Heřmánek: Logarithmic arithmetic core based RLS LATTICE implementation. Design, Automation and Test in Europe DATE 02, 271. IEEE, Los Alamitos 2002.
13. * Miroslav Líčko, Milan Tichý, Antonín Heřmánek, Rudolf Matoušek, Zdeněk Pohl: Prototyping of DSP algorithms on FPGA. POSTER 2002, 2. FEL ČVUT, Praha 2002.
14. * Rudolf Matoušek, Milan Tichý, Zdeněk Pohl, Jiří Kadlec, C. Softley: Logarithmic number system and floating-point arithmetics on FPGA. Lecture Notes in Computer Science. 2438. Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 627-636. Springer, Berlin 2002.
15. * Miroslav Líčko, B. Métais, Milan Tichý, Rudolf Matoušek: Extension for Xilinx System Generator - logarithmic arithmetic blockset. MATLAB 2002. Sborník příspěvků 10. ročníku konference, 280-284. VŠCHT, Praha 2002.
16. * Milan Tichý, Bohumil Kovář: Parallel factorised algorithms for mixture estimation. Artificial Neural Nets and Genetic Algorithms. Proceedings, 410-413. Springer, Wien 2001.

Other publications (16)
1. * Milan Tichý: ÚTIA spoluvyvíjí přijímač pro DVB-T2. Akademický bulletin AV ČR 10 (2009), 15-15. Středisko společných činností AV ČR, v. v. i..   Download
2. * Milan Tichý: Adaptive Filtering Algorithms Implementation and Evaluation of their Filtering Properties. Research Report 2164. ÚTIA AV ČR, Praha 2006.
3. * Milan Tichý: Efficient Floating-point-like Implementation of the (N)LMS and GSFAP Algorithms in FPGA. Research Report 2165. ÚTIA AV ČR, Praha 2006.
5. * Milan Tichý: Review and Classification of Adaptive Filtering Algorithms for the LNS Arithmetic. Research Report 2162. ÚTIA AV ČR, Praha 2006.
8. * Milan Tichý, A. Nisbet, D. Gregg: GSFAP adaptive filtering using log arithmetic for rescouse-constrained embedded systems. FPGA 2006. Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 236-236. Association for Computer Machinery, New York 2006.
10. * Milan Tichý: HSLA Package version 3.0.0. Matlab HSLA Toolbox 32- and 19-bit TWIN LNS ALU. Research Report 2086. ÚTIA AV ČR, Praha 2003.
11. * Zdeněk Pohl, Jiří Kadlec, Milan Tichý: RLS Lattice - Celoxica RC200 Demo. (Program). ÚTIA AV ČR, Praha 2003.
12. * Milan Tichý: HSLA Version 3.0.0 Evaluation Package. (Program). ÚTIA AV ČR, Praha 2003.
13. * Zdeněk Pohl, Jiří Kadlec, Miroslav Líčko, Rudolf Matoušek, Milan Tichý: Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program). ÚTIA AV ČR, Praha 2003.
14. * Milan Tichý: HSLA Version 4.0.0a Demo. (Program). ÚTIA AV ČR, Praha 2003.
15. * Milan Tichý: Adaptive Filtering Algorithms and the Logarithmic Number System Arithmetic. Research Report 2067. ÚTIA AV ČR, Praha 2002.
16. * Miroslav Líčko, Jan Schier, Zdeněk Pohl, Jiří Kadlec, Milan Tichý, Rudolf Matoušek, Antonín Heřmánek: Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping. Research Report 2069. ÚTIA AV ČR, Praha 2002.

Miscellaneous (5)
1. * Zdeněk Pohl, Milan Tichý: Self-adaptive LMS filter. 2009.
3. * Antonín Heřmánek, Tomáš Mazanec, Milan Tichý: DVB-T2 Receiver: Physical Layer Simulator. 2009.
4. * Jan Kloub, Tomáš Mazanec, Antonín Heřmánek, Milan Tichý: DVB-T2 Receiver Prototype: Physical Layer. 2009.
5. * Zdeněk Pohl, Jiří Kadlec, Milan Tichý: Adaptive Noise Canceller Demo based on the LS Lattice Filter. 2007.   Download