Department of Pattern Recognition

Research Report

RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic

Kadlec Jiří, Albu F., Softley Ch., Matoušek Rudolf, Heřmánek Antonín

: ÚTIA AV ČR, (Praha 2001)

: Research Report 2036

: AV0Z1075907

: HSLA 33544, ESPRIT, LN00B096, GA MŠk

: digital signal processing, logaritmic arithmetic, embedded compilation

: 09G, 09H

: JC