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1ET400750408
Matoušek Rudolf
,
Daněk Martin
,
Pohl Zdeněk
,
Bartosinski Roman
,
Honzík Petr
:
Reconfigurable System-on-a-Chip
,
Syndicated vol.5, 2 (2005), p. 1-3
[2005]
Kovář Bohumil
:
RIPAC Frontend - Metodologie tvorby bloků v Simulinku
,
( 2008)
[2008]
Kloub Jan
,
Schier Jan
:
Vyhodnocování růstu kolonií kvasinek Saccharomyces cerevisia s použitím akcelerátoru Uni1P/DX64
,
( 2008)
[2008]
Kovář Bohumil
,
Kloub Jan
,
Schier Jan
,
Heřmánek Antonín
:
Rapid Prototyping Platform For Reconfigurable Image Processing
,
Technical computing Prague 2008. 16th annual conference proceedings, p. 62-62
,
Technical Computing Prague 2008 /16./, (Praha, CZ, 11.11.2008-11.11.2008)
[2008]
Download
Kloub Jan
:
Aplikační příručka k vývojové desce Uni1P a modulům DX64
,
( 2008)
[2008]
Schier Jan
,
Kovář Bohumil
,
Zuzaňák J.
:
Configuration System for a DSP/FPGA-Based Embedded Accelerator
,
Digital Technologies 2007 Proceedings, p. 1-4 , Eds: Jarina Roman
,
Digital Technologies 2007, (Žilina, SK, 29.11.2007-30.11.2007)
[2007]
Kovář Bohumil
:
Detekce významných bodů v integrální hranové mapě
,
( 2007)
[2007]
Kovář Bohumil
,
Schier Jan
:
Kompresní algoritmy a jejich implementace
,
ÚTIA AV ČR, (Praha 2007)
Research Report 2191
[2007]
Kovář Bohumil
,
Schier Jan
:
Kompresní algoritmy a jejich implementace
,
( 2007)
[2007]
Kovář Bohumil
:
Detekce významných bodů v integrální hranové mapě
,
ÚTIA AV ČR, (Praha 2007)
Research Report 2186
[2007]
Schier Jan
,
Kovář Bohumil
,
Zemčík P.
,
Herout A.
,
Zuzaňák J.
:
Configuration System for a DSP/FPGA-Based Embedded Accelerator
,
Digital Technologies 2007 Book of Abstracts, p. 32-33 , Eds: Jarina Roman
,
Digital Technologies 2007, (Žilina, SK, 30.11.2007)
[2007]
Kovář Bohumil
,
Schier Jan
,
Zemčík P.
,
Herout A.
,
Zuzaňák J.
:
Simulink Model Converter for Embedded Video Accelerator
,
Technical Computing Prague 2007, p. 79-79
,
Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007)
[2007]
Pohl Zdeněk
:
Komunikace pro adm-xrc-4sx pomocí ZBIT pamětí
,
ÚTIA AV ČR, (Praha 2007)
[2007]
Schier Jan
,
Kovář Bohumil
:
A DSP/FPGA-based accelerator for video
,
Digital Technologies 2006, p. 1-5
,
Digital Technologies 2006, (Žilina, SK, 01.12.2006)
[2006]
Schier Jan
,
Kovář Bohumil
:
A DSP/FPGA-based accelerator for video processing
,
Digital Technologies 2006 Book of Abstracts, p. 13-13
,
Digital Technologies 2006, (Žilina, SK, 01.12.2006)
[2006]
Kovář Bohumil
,
Schier Jan
,
Zemčík P.
,
Herout A.
,
Beran V.
:
Simulink as Tool for Prototyping Reconfigurable Image Processing Applications
,
Technical computing Prague 2006. 14th annual conference proceedings, p. 52-57 , Eds: Procházka A.
,
Technical computing Prague 2006 /14./, (Prague, CZ, 26.10.2006)
[2006]
Zemčík P.
,
Herout A.
,
Beran V.
,
Fučík A.
,
Schier Jan
:
Reconfigurable image processing architecture
,
ICGST International Conference on Graphics, Vision and Image Processing. GVIP-05, p. 1-6
,
International Conference on Graphics, Vision and Image Processing, (Káhira, EG, 19.12.2005-21.12.2005)
[2005]
Schier Jan
,
Kovář Bohumil
,
Zemčík P.
,
Herout A.
,
Beran V.
:
Reconfigurable image processing architecture with simulink prototyping support
,
Technical Computing Prague 2005. 13th Annual Conference Proceeding, p. 1-4 , Eds: Moler C., Procházka A., Walden B.
,
MATLAB 05. Annual Conference of Technical Computing Prague 2005 /13./, (Praha, CZ, 15.11.2005)
[2005]
Schier Jan
,
Heřmánek Antonín
:
Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA
,
Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings, p. 1149-1151
,
International Conference FPL 2004 /14./, (Antverp, BE, 30.08.2004-01.09.2004)
[2004]
Heřmánek Antonín
,
Schier Jan
,
Regalia P.
:
Architecture design for FPGA implementation of finite interval CMA
,
Proceedings of the 12th European Signal Processing Conference, p. 1-4 , Eds: Hlawatsch F., Matz G., Rupp M.
,
EUSIPCO 2004 /12./, (Vienna, AT, 06.09.2004-10.09.2004)
[2004]
2019-01-07 08:39