(eng): We present design flow and related tool-chain supporting modeling, HW-SW co-simulation as well as generation of HDL code for reconfigurable MicroBlaze accelerators. Each accelerator is composed from reprogrammable PicoBlaze sequencing HW supported floating point processing batches executed on local data. The Xilinx MicroBlaze soft-core processor serves as the central CPU with access to the global off chip memory and peripherals. Each coprocessor can be re-programmed during runtime. This provides a framework for a partial dynamic change of the functionality of HW floating point accelerators suitable for FPGA as well as for the custom designs.

(cze): Článek presentuje metodologii návrhu rekonfigurovatelných akcelerátorů pro FPGA procesor MicroBlaze. Každý akcelerátor může být modifikován za chodu pomocí mikroprogramu.