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Conference Paper (international conference)
Fault classification for self-checking circuits implemented in FPGA
, , ,
: Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems, p. 228-231 , Eds: Takách G., Hlawiczka A., Sziray J.
: University of West Hungary, (Sopron 2005)
: IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./, (Sopron, HU, 13.04.2005-16.04.2005)
: CEZ:AV0Z10750506
: GA102/04/2137, GA ČR
: concurrent error detection, FPGA, ED codes
(eng): This work supports the design process of CED circuits implemented in FPGAs. We propose a new fault classification. We can summarize that our classification leads to a more accurate evaluation of the fault coverage, and we can determine whether the tested circuit satisfies the FS and ST properties. We can also evaluate how many considered faults violate the FS and ST property.
(cze): Článek se zabývá novou klasifikací poruch vhodnou pro samočinně kontrolované obvody. Poruchy jsou rozděleny podle jejich vlivu na bezpečnost proti poruchám a samočinnou kontrolu obvodu, a tak, na rozdíl od běžné klasifikace poruch, umožňuje přesněji vyhodnotit vlastnosti obvodu.
: 09G, 09H
: JC