Institute of Information Theory and Automation

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Ing. Jiří Kadlec, CSc.

Head of the department
Research interests: 
Recursive system identification algorithms suitable for FPGA; rapid prototyping of advanced signal processing algorithms; Scalable floating point arithmetic for FPGA SoC designs
Publications ÚTIA: 
2021-12-14 11:17

Person detail

Duration: 2023 - 2026
The main aim of the EECONE project is to reduce e-waste on a European scale. The environmental impact arising from e-waste can thus be reduced by working in three principal areas: 1) Increase service lifetime of electronic products by application of ecodesign guidelines for increasing their reliability and their repair rate, thereby reducing the volume of e-waste.
Duration: 2021 - 2024
The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main cha
Duration: 2019 - 2022
Arrowhead Tools is Europe's largest project for solutions in automation and digitization for the industry. The purpose of the three-year project Arrowhead Tools is to create engineering tools for the next generation of solutions in digitization and automation for the European industry.
Duration: 2018 - 2021
The objective of FitOptiVis is to develop a cross-domain approach for smart integration of image- and video-processing pipelines for CPS covering a reference architecture, supported by low-power, high-performance, smart devices, and by methods and tools for combined design-time and run-time multi-objective optimisation within system and environment constraints.
Duration: 2018 - 2021
The WAKEMEUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains. The already defined microcontrollers with 40nm embedded flash technology will be consolidated to build a solid manufacturing platform.
Duration: 2017 - 2020
SILENSE is an ECSEL JU standard (RIA) project. The SILENSE project will focus on using smart acoustic technologies and ultrasound in particular for Human Machine- and Machine to Machine Interfaces. Acoustic technologies have the main advantage of a much simpler, smaller, cheaper and easier to integrate transducer.



Ing. Roman Bartosinski Ph.D.
Ing. Petr Honzík Ph.D.
Ing. Zdeněk Pohl Ph.D.