(eng): Implementation of IEEE floating point in FPGA (Field Programmable Gate Array)is not easy and therefore many advanced DSP and control algorithms make it to FPGA with considerable delays. This paper presents one of possible solution based on a 32-bit logarithmic ALU, in the form of an FPGA core compatible with the Handel C 2.1 and the new DK1 tool from Celoxica. This research is performed under the EU ESPRIT 33544 HSLA Long-term research project, coordinated by the University of Newcastle.