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Conference Paper (international conference)
FPGA implementation of the adaptive lattice filter
, ,
: Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D.
: Springer, (Berlin 2003)
:
: Field Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003)
: CEZ:AV0Z1075907
: IST-2001-34016, EU IST, LN00B096, GA MŠk
: FPGA, logarithmic numbering system, floating-point signal processor
(eng): This paper presents the FPGA implementation of a noise canceler with an adaptive RLS-Lattice filter in Xilinx devices. Since this algorithm requires floating-point computations, Logarithmic Numbering System (LNS) has been used. The pipelined lattice filter macro and input/output conversion routines has been designed. The implementation results are compared with an implementation on 32-bit IEEE floating-point signal processor.
: 09G, 09H
: JC